EVG-RF-2 – Event Timing Generator​

Product Overview ​

The EVG-RF-2 chassis is capable of generating several MRF compatible event timing data streams based on up to two external RF reference clocks, or an internal clock.  It may also bring in 16 LVTTL logic signals.  This entirely Open Hardware design is based around the LBL Marble dual FMC carrier board.  Configure, control, and monitor over 1Gbps ethernet.

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Key Features

  • EPICS Driver – Time series data and FFT to clients at 20Hz
  • EPICS Driver – Quartz state of health monitoring
  • EPICS – Configuration, control and monitoring of DAQ
  • Accepts up to two independent RF reference clocks
  • Generates independent event streams with different bit rates
  • Each 8 fiber outputs may be dedicated to one event stream
  • Internal coincidence detector
  • 11 LVTTL inputs may trigger events on either event stream
  • One LVTTL input dedicated for GPS/GNSS pulse-per-second

Key Filmware Features

  • Bring your own! Use of Osprey stock firmware is optional. Replace with yours.
  • Dedicated GPS/GNSS pulse-per-second (PPS) input.
  • NTPv3 client to fetch timestamp to distribute
  • Configure LVTTL inputs to send upstream events or distributed bus bits
  • Control/monitor with LBL LEEP/UDP protocol
  • EPICS Driver – Available!

OSH Timing Ecosystem

The EVG-RF-2 will be used as part of an MRF compatible event timing system.

Front Panel

  • RJ45 1Gbps Ethernet
  • 2x SMA-F Reference clock inputs
  • 1 SMA-F 50 ohm (GPS/GNSS PPS)
  • 15x SMA-F 100K ohm (triggers, …)
  • 8x LC multi-mode fiber tranceivers.
  • Micro USB-B debug/programming connector
  • Power input

The Osprey EVG-Timing-Event Distribution is based on a Marble Dual FMC Carrier Board with a low jitter Clock Generator with alignment to external or internal RF reference clocks. The event distribution use the MRF protocol to distribute event codes, dbus (clocks), and a global wall clock time (POSIX).  The chassis houses an RF Input FMC attached to a Marble carrier developed by Berkeley National Laboratory.

Technical Parameter

Clocking resources

  • Local 125 MHz crystal oscillator
  • 2x RF inputs on MGT clock capable inputs

Back Panel

  • Ethernet
  • Power button
  • Power in 12V
  • 1x grounding connector

Programmable resources on Marble

  • Kintex FPGA FF676

Memory

  • SODIMM socket (Optional)
  • 8MB boot flash

Other

  • Protocols: UDP/IP, LEEP, NTPv3
  • 1x FPGA JTAG connector
  • Power supply

Front Panel

  • 2 SMA connectors for RF clock references. Signal level range 0 → 10 dBm.
  • 1 SMA connector for PPS marker. TTL, 50Ω.
  • 11 SMA connectors configurable as hardware triggers or distributed bus. TTL, 100KΩ
  • 8 Dual LC-50 multi-mode fiber links
  • Event link on outgoing fibers.
  • MPS and round-trip latency on incoming fibers.
  • 1 Power STS LED

I/O Modules

  • 2 FMC Connectors

Software

  • EPICS Drivers in Linux

Support

We offer electronics engineering consultancy services, including: custom modifications of hardware, custom firmware and gateware modifications, system design, integration and testing.