Data Acquisition System

Product Overview ​

The Osprey DAQ-32-250-24 is a highly scalable data acquisition system designed for facility-wide synchronous sampling. By utilizing a GPS receiver and fiber timing network, the system synchronizes all distributed nodes to provide time-stamped data for configurations scaling up to 1,024 signals at 250 kHz. The infrastructure supports event-based and on-demand acquisition, and high-speed machine protection. At the node level, each 2U rack-mount chassis provides 32-channels of 24-bit resolution analog digitization. Serving as a high-density I/O front end, the chassis integrates seamlessly into the broader timing network to ensure reliable, precision data collection across the entire facility.

Product Overview

The chassis utilizes an LBL Marble FPGA carrier with dual 16-channel ADC FMCs, providing 32 different inputs with configurable AC/DC coupling. High-bandwidth fiber and Ethernet channels support deterministic data streaming, while firmware enables phase-aligned sampling across all nodes. Fully integrated with EPICS, the system provides seamless global clocking and remote management.

Key Features

Proven Reliability

Successfully deployed at the NASA SEC facility to provide data acquisition for the Artemis capsule testing program.

Basic Architecture

The Osprey Quartz ADC board contains four Analog Devices AD7768 ADCs around which the rest of the board is built. Inputs at the DB-37 connectors are scaled and pass through filtering and a per-channel selectable DC blocking stage before being sent to an ADC. The ADC then streams its data via LVDS through the FMC connectors to the Marble board.

The Marble board is built around a Kintex 160T 7 Series FPGA. This is one of the highest performing FPGAs available from AMD while allowing use of the license-free tool chain. The Marble board is responsible for monitoring, packaging, reporting, and synchronizing all events and triggers from various nodes.

The Osprey DAQ system is a distributed star network. A central GPS receiver and fiber timing network provide unified clock reference.

System Capabilities

Chassis Overview

Front Panel

Back Panel

Internal Architecture

Tech Specs

Nominal Performance

Absolute Performance

Other Specs